• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    A semiconductor device for manufacturing a semiconductor memory cell includes the steps of: a) preparing an active matrix provided with at least one transistor, a plurality of conductive plugs electrically connected to the transistors and an insulating layer formed around the conductive plugs; b) forming a supporting layer, made of carbon, on top of the active matrix and patterned into a predetermined configuration, thereby obtaining a patterned supporting layer; c) forming bottom electrodes on the patterned supporting layer; and d) removing the patterned supporting layer.
    公开号:US20010006837A1
    申请号:US09/735,626
    申请日:2000-12-14
    公开日:2001-07-05
    发明作者:Se-Han Kwon；Jang-Yup Kim
    申请人:Hynix Semiconductor Inc；
    IPC主号:H01L27-10852
    专利说明:
    [0001] The present invention relates to a semiconductor device; and, more particularly, to a method for manufacturing a semiconductor memory device incorporating therein textured electrodes for implementing a high-density storage capacitor. [0001] DESCRIPTION OF THE PRIOR ART
    [0002] As is well known, a dynamic random access memory (DRAM) with at least one memory cell comprised of a transistor and a capacitor has a higher degree of integration mainly by downsizing through micronization. However, there is still a demand for downsizing the area of the memory cell. [0002]
    [0003] To meet the demand, therefore, there have been proposed several methods, such as a trench type or a stack type capacitor, which is arranged three-dimensionally in a memory device to reduce the cell area available to the capacitor. However, the process of manufacturing three-dimensionally arranged capacitor is a long and tedious one and consequently involves high manufacturing cost. Therefore, there is a strong demand for a new memory device that can reduce the cell area with securing a requisite volume of information without requiring complex manufacturing steps. [0003]
    [0004] In attempt to meet the demand, there have been proposed a high-density dynamic random access memory (DRAM) which incorporates bottom electrodes having textured surface morphology by forming hemispherical grain (HSG) thereon. [0004]
    [0005] One of the major shortcomings of the above-described high-density DRAM is that it requires processes for forming a nitride layer and a buffer oxide layer as an etching stop layer during the formation of the bottom electrodes. [0005] SUMMARY OF THE INVENTION
    [0006] It is, therefore, an object of the present invention to provide a method for manufacturing a semiconductor device capable of simplifying the manufacturing steps thereof by incorporating therein a carbon layer as a supporting layer. [0006]
    [0007] In accordance with one aspect of the present invention, there is provided a method for manufacturing a semiconductor device for use in a memory cell, the method comprising the steps of: a) preparing an active matrix provided with at least one transistor, a plurality of conductive plugs electrically connected to the transistors and an insulating layer formed around the conductive plugs; b) forming a supporting layer, made of carbon, on top of the active matrix and patterned into a predetermined configuration, thereby obtaining a patterned supporting layer; c) forming bottom electrodes on the patterned supporting layer; d) removing the patterned supporting layer; e) forming hemispherical grains (HSGs) on surfaces of the bottom electrodes; f) forming capacitor dielectric films on top of the bottom electrodes; and g) forming top electrodes on top of the capacitor dielectric films, thereby obtaining a capacitor. [0007] BRIEF DESCRIPTION OF THE DRAWINGS
    [0008] The above and other objects and features of the present invention will become apparent from the following description of the preferred embodiments given in conjunction with the accompanying drawings, in which: [0008]
    [0009] FIG. 1 is a cross sectional view setting forth a semiconductor device in accordance with the present invention; and [0009]
    [0010] FIGS. 2A to [0010] 2F are schematic cross sectional views setting forth a method for the manufacture of the semiconductor memory device in accordance with the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
    [0011] There are provided in FIGS. 1 and 2A to [0011] 2F a cross sectional view of a semiconductor device 100 for use in a memory cell and cross sectional views setting forth a method for the manufacture thereof in accordance with preferred embodiments of the present invention. It should be noted that like parts appearing in FIGS. 1 and 2A to 2F are represented by like reference numerals.
    [0012] In FIG. 1, there is provided a cross sectional view of the inventive semiconductor device [0012] 100 comprising an active matrix 10, bottom electrodes 25 provided with hemispherical grains (HSGs) 26, a capacitor dielectric layer 28 and a top electrode layer 30. The active matrix 10 includes a silicon substrate 2, transistors formed on top of the silicon substrate 2, an isolation region 4 for isolating the transistors, poly plugs 16, a bit line 18 and word lines 20. Each of the transistors has diffusion regions 6, a gate oxide 8, a gate line 12 and a side wall 14.
    [0013] In the semiconductor device [0013] 100, the bit line 18 is electrically connected to one of the diffusion regions 6 to apply an electric potential. Each of the bottom electrodes 26 is electrically connected to the other diffusion regions 6 through the poly plugs 16. Although the bit line 18 actually extends in right and left directions bypassing the poly plugs 16, the drawing does not show these parts of the bit line 18. It is preferable that the bottom electrodes 25 are made of a material such as polysilicon, amorphous silicon (a—Si) or the like. And also, each of the bottom electrodes 26 has a textured surface to enlarge the electrode surface area without increasing the lateral dimensions thereof.
    [0014] FIGS. 2A to [0014] 4F are schematic cross sectional views setting forth the method for manufacture of a semiconductor memory device 100 in accordance with the present invention.
    [0015] The process for manufacturing the semiconductor device [0015] 100 begins with the preparation of an active matrix 10 including a silicon substrate 2, an isolation region 4, diffusion regions 6, gate oxides 8, gate lines 12, side walls 14, a bit line 18, poly plugs 16 and an insulating layer 22, as shown in FIG. 2A. The bit line 18 is electrically connected to one of the diffusion regions 6 to apply an electric potential. Each of the poly plugs 16 is electrically connected to the other diffusion regions 6, respectively. Although the bit line 18 actually extends in right and left directions bypassing the poly plugs 16, the drawing does not show these parts of the bit line 18. The insulating layer 22 is made of a material, e.g., boron-phosphor-silicate glass (BPSG).
    [0016] In an ensuing step, a supporting layer, e.g., made of carbon, is formed on top of the active matrix [0016] 10 by using a method such as a chemical vapor deposition (CVD) or a physical vapor deposition (PVD) and patterned into a predetermined configuration, thereby obtaining a patterned supporting layer 24, as shown in FIG. 2B. If the supporting layer is made of oxide and an etching stop layer is made of nitride, there is occurred a punch effect during the etching of the supporting layer due to its low etching ratio between the supporting layer and the etching stop layer. In the preferred embodiment, the present invention employs a carbon layer as a supporting layer to prevent the active matrix 10 from the attack during the etching of the supporting layer without forming an additional etching stop layer. This is achieved by utilizing an O2 gas as an etchant gas.
    [0017] In a following step, a conductive layer [0017] 23 is formed on top of the patterned supporting layer 24 and the active matrix 10, as shown in FIG. 2C. Preferably, the conductive layer 25 is made of a material selected from a group consisting of amorphous silicon, poly silicon, Ta2O5 and TiN. In the preferred embodiment, the conductive layer 23 has a thickness ranging from approximately 400 Å to approximately 700 Å.
    [0018] In the next step, a photoresist layer (not shown) is formed on the entire surface of the conductive layer [0018] 23. The photoresist layer has a thickness ranging from approximately 8,000 Å to approximately 15,500 Å. And then, the photoresist layer and the conductive layer 23 are planarized by using a method such as a chemical mechanical polishing (CMP) or the like until the patterned supporting layer 24 is exposed. Thereafter, the patterned supporting layer 24 are removed by using a dry etching, thereby obtaining bottom electrode structures 25, as shown in FIG. 2D. In this case, the dry etching utilizes an O2 gas as a reaction gas. It is possible that the patterned supporting layer 24 can be removed by using an etch-back process.
    [0019] In an ensuing step, the bottom electrode structures [0019] 25 are carried out by a seeding and an annealing processes to produce a rugged surface which has relatively large polycrystalline silicon grains of about 50 to about 250 nm, thereby obtaining bottom electrodes 26, as shown in FIG. 2E. The annealing process can include the step of dispersing a material such as polysilicon or silicon dioxide on the surfaces of the bottom electrode structures 25 for producing nucleation sites. And also, the annealing process can include the step of accumulating silicon at the nucleation sites, thereby forming the rugged surface having a rough surface morphology. The resulting surface morphology is usually comprised of relatively large polycrystallites, referred as hemispherical grain (HSG) silicon.
    [0020] Thereafter, a capacitor dielectric layer [0020] 28 and a top electrode layer 30 are formed on top of the bottom electrodes 26, successively, as shown in FIG. 2F.
    [0021] By utilizing a carbon layer as a supporting layer, the present invention can manufacture a semiconductor memory device without forming an etch stop layer on top of the active matrix. [0021]
    [0022] While the present invention has been described with respect to the particular embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the scope of the invention as defined in the following claims. [0022]
    权利要求:
    Claims (9)
    [1" id="US-20010006837-A1-CLM-00001] 1. A method for manufacturing a semiconductor device for use in a memory cell, the method comprising the steps of:
    a) preparing an active matrix provided with at least one transistor, a plurality of conductive plugs electrically connected to the transistors and an insulating layer formed around the conductive plugs;
    b) forming a supporting layer, made of carbon, on top of the active matrix and patterned into a predetermined configuration, thereby obtaining a patterned supporting layer;
    c) forming bottom electrodes on the patterned supporting layer; and
    d) removing the patterned supporting layer.
    [2" id="US-20010006837-A1-CLM-00002] 2. The method of
    claim 1 , wherein the insulating layer includes boron phosphor silicate glass (BPSG).
    [3" id="US-20010006837-A1-CLM-00003] 3. The method of
    claim 2 , wherein the supporting layer formed by using a chemical vapor deposition (CVD).
    [4" id="US-20010006837-A1-CLM-00004] 4. The method of
    claim 3 , wherein the supporting layer has a thickness ranging from approximately 8,000 Å to 15,000 Å.
    [5" id="US-20010006837-A1-CLM-00005] 5. The method of
    claim 1 , wherein the step e) includes the steps of:
    d1) forming a plasma by using an oxygen gas, thereby obtaining a O2 plasma; and
    d2) reacting the patterned supporting layer with the O2 plasma, thereby removing the patterned supporting layer.
    [6" id="US-20010006837-A1-CLM-00006] 6. The method of
    claim 1 , wherein the conductive layer includes a material selected from a group consisting of amorphous silicon, poly silicon, Ta2O5 and TiN.
    [7" id="US-20010006837-A1-CLM-00007] 7. The method of
    claim 6 , after the step d), further comprising the step of:
    e) forming hemispherical grains (HSGs) on surfaces of the bottom electrodes.
    [8" id="US-20010006837-A1-CLM-00008] 8. The method of
    claim 7 , wherein the conductive layer has a thickness ranging from approximately 400 Å to 700 Å.
    [9" id="US-20010006837-A1-CLM-00009] 9. The method of
    claim 7 , after the step e), further comprising the steps of:
    forming capacitor dielectric films on top of the bottom electrodes; and
    forming top electrodes on top of the capacitor dielectric films, thereby obtaining a capacitor.
    类似技术:
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    同族专利:
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    KR20010059284A|2001-07-06|
    US6444538B2|2002-09-03|
    引用文献:
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    US6518612B2|1999-12-30|2003-02-11|Hyundai Electronics Industries Co., Ltd.|Semiconductor memory device using hemispherical grain silicon for bottom electrodes|
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    US20070034928A1|2005-08-10|2007-02-15|Micron Technology, Inc.|Capacitor structure for two-transistor dram memory cell and method of forming same|US3639121A|1969-03-03|1972-02-01|Eastman Kodak Co|Novel conducting lacquers for electrophotographic elements|
    DE2227751B2|1972-06-07|1979-02-08|Siemens Ag, 1000 Berlin Und 8000 Muenchen|Electric capacitor and process for its manufacture|
    JP2681298B2|1989-03-20|1997-11-26|富士通株式会社|Method for manufacturing semiconductor memory device|
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    JP2817645B2|1995-01-25|1998-10-30|日本電気株式会社|Method for manufacturing semiconductor device|
    US5612558A|1995-11-15|1997-03-18|Micron Technology, Inc.|Hemispherical grained silicon on refractory metal nitride|
    JP3230663B2|1998-03-27|2001-11-19|日本電気株式会社|Manufacturing method of cylindrical stack electrode|
    JPH11289063A|1998-04-03|1999-10-19|Matsushita Electron Corp|Manufacture of semiconductor device|
    JP3905977B2|1998-05-22|2007-04-18|株式会社東芝|Manufacturing method of semiconductor device|
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    US6888217B2|2001-08-30|2005-05-03|Micron Technology, Inc.|Capacitor for use in an integrated circuit|
    KR100539268B1|2004-06-24|2005-12-27|삼성전자주식회사|Method of manufacturing semiconductor memory device|
    法律状态:
    2001-03-12| AS| Assignment|Owner name: HYUNDAI ELECTRONICS INDUSTRIES CO., LTD., KOREA, R Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KWON, SE-HAN;KIM, JANG-YUP;REEL/FRAME:011581/0841 Effective date: 20001205 |
    2002-08-15| STCF| Information on status: patent grant|Free format text: PATENTED CASE |
    2003-07-08| CC| Certificate of correction|
    2006-02-03| FPAY| Fee payment|Year of fee payment: 4 |
    2010-02-26| FPAY| Fee payment|Year of fee payment: 8 |
    2013-05-23| AS| Assignment|Owner name: HYNIX SEMICONDUCTOR INC., KOREA, REPUBLIC OF Free format text: CHANGE OF NAME;ASSIGNOR:HYUNDAI ELECTRONICS INDUSTRIES CO., LTD;REEL/FRAME:030490/0238 Effective date: 20010406 Owner name: SK HYNIX INC., KOREA, REPUBLIC OF Free format text: CHANGE OF NAME AND ADDRESS;ASSIGNOR:HYNIX SEMICONDUCTOR INC.;REEL/FRAME:030490/0258 Effective date: 20120402 Owner name: INTELLECTUAL DISCOVERY CO. LTD., KOREA, REPUBLIC O Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SK HYNIX INC.;REEL/FRAME:030471/0480 Effective date: 20130319 |
    2014-03-03| FPAY| Fee payment|Year of fee payment: 12 |
    优先权:
    申请号 | 申请日 | 专利标题
    KR1999-66676||1999-12-30||
    KR1019990066676A|KR20010059284A|1999-12-30|1999-12-30|A method for forming a capacitor of a semiconductor device|
    KR99-66676||1999-12-30||
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